Attila Zsigmond

Angestellt, ASIC Design Engineer, Intel Deutschland GmbH

Munich, Deutschland

Fähigkeiten und Kenntnisse

RTL Design (not main focus though)
SDC
Digital Synthesis (Synopsys DC)
Simulations (RTL functional & back-annotated netli
Floorplanning
Placement
Routing
Extraction and STA
Formal Verification
Customer Support
TCL / Perl
Digital Design Implementation (RTL to GDS)
Innovus
tempus
quantus
PNR
STA

Werdegang

Berufserfahrung von Attila Zsigmond

  • Bis heute 2 Jahre und 7 Monate, seit Nov. 2021

    ASIC Design Engineer

    Intel Deutschland GmbH
  • 3 Jahre und 1 Monat, Okt. 2018 - Okt. 2021

    Lead Application Engineer

    Cadence Design Systems, Inc.

  • 1 Jahr und 5 Monate, Mai 2017 - Sep. 2018

    ASIC Development Engineer

    ZF Group

    Providing technical expertise and project management services for the “Sensors Team” for a mixed signal ASIC project developed in partnership with a third-party provider. Main technical interface between ZF-TRW Team and ASIC provider.

  • 6 Monate, Okt. 2016 - März 2017

    Synthesis and FV Engineer - Contractor

    Renesas Electronics Europe GmbH

    - Digital Synthesis with Cadance RC on advanced process nodes (16 nm) - Formal Verification LEC / Formality - SDC analysis with Synopsys GCA - Flow optimization

  • 4 Jahre und 2 Monate, Aug. 2012 - Sep. 2016

    Digital Design Engineer / Customer Application Engineer

    eASIC Corp.

    - Implementation of digital design on eASIC's proprietary structured ASICs (28nm and 45nm), from RTL to GDSII, thus having a comprehensive understanding of all digital design steps - Responsible for technical customer support during whole project life cycle, often offering on-site support

  • 9 Monate, Nov. 2011 - Juli 2012

    Intern

    eASIC Corp.

  • 3 Monate, Sep. 2011 - Nov. 2011

    Rework Technician

    Benchmark Electronics

    PCB level debug on high complexity products.

Ausbildung von Attila Zsigmond

  • 1 Jahr und 10 Monate, Okt. 2011 - Juli 2013

    Telecommunication and Electrical Engineering

    "Transilvania" University of Brasov

  • 3 Jahre und 10 Monate, Okt. 2007 - Juli 2011

    Telecommunications and Electrical Engineering

    "Transilvania" University of Brasov

Sprachen

  • Ungarisch

    Muttersprache

  • Rumänisch

    Muttersprache

  • Englisch

    Fließend

  • Deutsch

    Grundlagen

Interessen

Reading
Hobby electronics
Travel

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